Freescale Semiconductor DSP56364 Manuel d'utilisateur

Document Number: DSP56364UMRev. 208/2006DSP56364 24-Bit Digital SignalProcessorUsers Manual

BookTitle, Rev. #x Freescale Semiconductor

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-36 Freescale Semiconductor 6.3.6.5 SAISR Receive Frame Sync Flag

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-37 6.3.6.10 SAISR Transmit Frame Sync Fla

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-38 Freescale Semiconductor 6.3.6.14 SAISR Transmit Odd-Data Regis

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-39 Figure 6-13 ESAI Data Path Programmin

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-40 Freescale Semiconductor Figure 6-14 ESAI Data Path Programmin

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-41 6.3.7 ESAI Receive Shift RegistersThe

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-42 Freescale Semiconductor transmitter empty condition (TDE=1), o

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-43 After hardware or software reset, the

Operating ModesDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-44 Freescale Semiconductor When bit number N in the RSM is set, the rece

Operating ModesDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-45 NOTEIf the ESAI receiver section is already o

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor xi Figure 1-1 DSP56364 Block Diagram . . . . . . . . . . . . . .

Operating ModesDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-46 Freescale Semiconductor the previous setting and the new frame is ser

Operating ModesDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-47 or they may have their own separate clock and

GPIO - Pins and RegistersDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-48 Freescale Semiconductor programming RSHFD bit in the RCR re

GPIO - Pins and RegistersDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-49 6.5.2 Port C Direction Register (PR

ESAI Initialization ExamplesDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-50 Freescale Semiconductor configured as GPIO. If a port pi

ESAI Initialization ExamplesDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-51 6.6.2 Initializing Just the ESAI

ESAI Initialization ExamplesDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-52 Freescale Semiconductor NOTES

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 7-1 7 Serial Host Interface7.1 IntroductionThe Serial Host Interf

Serial Host Interface Internal ArchitectureDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 27-2 Freescale Semiconductor 7.2 Serial Host In

SHI Clock GeneratorDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 7-3 7.3 SHI Clock GeneratorThe SHI clock gener

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2xii Freescale Semiconductor Figure C-2 Operating Mode Register (OMR) . . . . . . . . .

Serial Host Interface Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 27-4 Freescale Semiconductor Figure 7-4 SHI Progra

Serial Host Interface Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 7-5 The interrupt vector t

Serial Host Interface Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 27-6 Freescale Semiconductor Figure 7-5 SHI I/O Sh

Serial Host Interface Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 7-7 7.4.4.1 HSAR Reserved

Serial Host Interface Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 27-8 Freescale Semiconductor Figure 7-6 SPI Data-T

Serial Host Interface Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 7-9 When in Master mode an

Serial Host Interface Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 27-10 Freescale Semiconductor When HFM[1:0] are cle

Serial Host Interface Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 7-11 7.4.6.1.1 SHI Individ

Serial Host Interface Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 27-12 Freescale Semiconductor It is recommended tha

Serial Host Interface Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 7-13 7.4.6.9 HCSR Idle (HI

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor xiii Table 2-1 DSP56364 Functional Signal Groupings . . . . . .

Serial Host Interface Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 27-14 Freescale Semiconductor NOTEClearing HBIE wil

Serial Host Interface Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 7-15 NOTEClearing HRIE[1:0

SPI Bus CharacteristicsDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 27-16 Freescale Semiconductor 7.4.6.16 Host Receive FIFO Full (HRFF

I2C Bus CharacteristicsDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 7-17 the master data input line, and MOSI

I2C Bus CharacteristicsDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 27-18 Freescale Semiconductor • Stop data transfer—The stop event i

I2C Bus CharacteristicsDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 7-19 the slave device is ready for the nex

SHI Programming ConsiderationsDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 27-20 Freescale Semiconductor 7.7 SHI Programming Considerat

SHI Programming ConsiderationsDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 7-21 7.7.2 SPI Master ModeThe SPI M

SHI Programming ConsiderationsDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 27-22 Freescale Semiconductor • SCK/SCL is the SCL serial cl

SHI Programming ConsiderationsDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 7-23 7.7.3.2 Transmit Data In I2C S

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2xiv Freescale Semiconductor

SHI Programming ConsiderationsDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 27-24 Freescale Semiconductor In the I2C Master mode, a data

SHI Programming ConsiderationsDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 7-25 In a receive session, only the

SHI Programming ConsiderationsDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 27-26 Freescale Semiconductor NOTES

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor A-1 Appendix A Bootstrap ROMA.1 DSP56364 Bootstrap Program; BOOTS

Bootstrap ROMDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2A-2 Freescale Semiconductor opt cex,mex,mu;;;;;;;;;;;;;;;;;;;;;;

Bootstrap ROMDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor A-3 ; MD:MC:MB:MA=1110 - Bootstrap from SHI (I2C sla

Bootstrap ROMDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2A-4 Freescale Semiconductor ;=======================================

Bootstrap ROMDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor A-5 bra <* ;=======================

Bootstrap ROMDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2A-6 Freescale Semiconductor ;; write pattern to all memory

Bootstrap ROMDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor A-7 eor x1,a add

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor xv PrefaceThis manual contains the following sections and appendi

Bootstrap ROMDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2A-8 Freescale Semiconductor dc * endm

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor B-1 Appendix B BDSL FileB.1 BSDL FILE-- M O T O R O L A S S D T

BDSL FileDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2B-2 Freescale Semiconductor EXTAL: in bit; TA_N: in bit; CAS_N:

BDSL FileDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor B-3 "PVCC: 31, " & &

BDSL FileDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2B-4 Freescale Semiconductor attribute BOUNDARY_LENGTH of DSP56364 : entity is 86

BDSL FileDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor B-5 "46 (BC_1, TA_N, input, X),&q

BDSL FileDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2B-6 Freescale Semiconductor

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor C-1 Appendix C Programmer’s ReferenceC.1 IntroductionThis section

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2C-2 Freescale Semiconductor DMA $FFFFF4 DMA STATUS REGISTER (DSTR)

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor C-3 Reserved $FFFFD7 thru $FFFFD0 RESERVED

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2xvi Freescale Semiconductor Manual ConventionsThe following conventions are used in this

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2C-4 Freescale Semiconductor ESAI $FFFFBC ESAI RECEIVE SLOT MASK REG

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor C-5 Reserved $FFFF9F thru $FFFF95 RESERVEDS

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2C-6 Freescale Semiconductor VBA:$2E 0 - 2 ReservedVBA:$30 0 - 2 ESA

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor C-7 IRQD (External Interrupt)DMA Channel 0

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2C-8 Freescale Semiconductor C.2 Programming SheetsThe following wor

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor C-9 Figure C-1. Status Register (SR)Applica

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2C-10 Freescale Semiconductor Figure C-2. Operating Mode Register (O

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor C-11 Figure C-3. Interrupt Priority Registe

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2C-12 Freescale Semiconductor Figure C-4. Interrupt Priority Registe

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor C-13 Figure C-5. Phase Lock Loop Control Re

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor xvii — the reset instruction, written as “RESET,”— the reset oper

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2C-14 Freescale Semiconductor Figure C-6. SHI Slave Address (HSAR) a

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor C-15 Figure C-7. SHI Host Transmit Data Reg

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2C-16 Freescale Semiconductor Figure C-8. SHI Host Control/Status Re

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor C-17 Figure C-9. ESAI Transmit Clock Contro

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2C-18 Freescale Semiconductor Figure C-10. ESAI Transmit Clock Contr

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor C-19 Figure C-11. ESAI Receive Clock Contro

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2C-20 Freescale Semiconductor Figure C-12. ESAI Receive Clock Contro

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor C-21 Figure C-13. ESAI Common Control Regis

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2C-22 Freescale Semiconductor Figure C-14. ESAI Status Register (S

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor C-23 Figure C-15. Port B Registers (PCRB, P

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2xviii Freescale Semiconductor

Programmer’s ReferenceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2C-24 Freescale Semiconductor Figure C-16. Port C Registers (PCRC, P

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor Index-1 IndexAaddermodulo 1-5offset 1-5reverse-carry 1-5Address A

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Index-2 Freescale Semiconductor Receive Interrupt Enable Bits 7-14SHI Control/Status Regi

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor Index-3 PPAB 1-7PAG 1-6PC register 1-6PCU 1-6PDB 1-7PDC 1-6Periph

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Index-4 Freescale Semiconductor Sixteen-bit Compatibility 3-1Size register (SZ) 1-6SP 1-6

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 1-1 1 Overview1.1 IntroductionThe DSP56364 24-Bit Digital Signal

How to Reach Us:Home Page:www.freescale.comE-mail:[email protected]/Europe or Locations Not Listed:Freescale SemiconductorTechnical Informati

FeaturesDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 21-2 Freescale Semiconductor Figure 1-1 DSP56364 Block Diagram1.2 Features• DSP56

Audio Processor ArchitectureDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 1-3 — Very low-power CMOS design, ful

Core DescriptionDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 21-4 Freescale Semiconductor 1.4 Core DescriptionThe DSP56364 uses the DSP

DSP56300 Core Functional BlocksDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 1-5 1.5.1.1 Data ALU RegistersThe

DSP56300 Core Functional BlocksDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 21-6 Freescale Semiconductor 1.5.3 Program Control Unit (PC

DSP56300 Core Functional BlocksDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 1-7 • Y memory expansion bus (YM_E

Data and Program memoryDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 21-8 Freescale Semiconductor 1.5.7 JTAG TAP and OnCE ModuleThe DSP5

Internal I/O Memory MapDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 1-9 memory switch can be accomplished prov

Status Register (SR)DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 21-10 Freescale Semiconductor 1.8 Status Register (SR)Refer to the DSP

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 2-1 2 Signal/Connection Descriptions2.1 Signal GroupingsThe input

BookTitle, Rev. #Freescale Semiconductor iii Manual Conventions1 Overview1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal GroupingsDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 22-2 Freescale Semiconductor Figure 2-1 Signals Identified by Functional

PowerDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 2-3 2.2 Power2.3 GroundTable 2-2 Power InputsPower Name De

Clock and PLLDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 22-4 Freescale Semiconductor 2.4 Clock and PLL2.5 External Memory Expansion P

External Memory Expansion Port (Port A)DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 2-5 2.5.2 External Data Bu

Interrupt and Mode ControlDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 22-6 Freescale Semiconductor 2.6 Interrupt and Mode ControlThe i

Serial Host InterfaceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 2-7 2.7 Serial Host InterfaceThe SHI has fiv

Serial Host InterfaceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 22-8 Freescale Semiconductor .Table 2-9 Serial Host Interface Signa

Serial Host InterfaceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 2-9 MOSI Input or outputTri-stated SPI Maste

Enhanced Serial Audio InterfaceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 22-10 Freescale Semiconductor 2.8 Enhanced Serial Audio Int

Enhanced Serial Audio InterfaceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 2-11 FST Input or output GPIO disc

BookTitle, Rev. #iv Freescale Semiconductor 3 Memory Configuration3.1 Memory Spaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Enhanced Serial Audio InterfaceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 22-12 Freescale Semiconductor SDO5 Output GPIO disconnected

JTAG/OnCE InterfaceDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 2-13 2.9 JTAG/OnCE InterfaceSDO1 Output GPIO d

GPIO SignalsDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 22-14 Freescale Semiconductor 2.10 GPIO SignalsTable 2-12 GPIO SignalsSignal

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 3-1 3 Memory Configuration3.1 Memory SpacesThe DSP56364 provides

Memory SpacesDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 23-2 Freescale Semiconductor Customer code should not use this area. The cont

Memory Space ConfigurationDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 3-3 3.1.2.2 X Data RAMThe on-chip X dat

Internal Memory ConfigurationDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 23-4 Freescale Semiconductor Memory maps for the different co

Internal Memory ConfigurationDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 3-5 3.3.3 Dynamic Memory Configurati

Memory MapsDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 23-6 Freescale Semiconductor 3.4 Memory MapsFigure 3-1 Memory Maps for MS=0, S

Memory MapsDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 3-7 Figure 3-3 Memory Maps for MS=0, SC=1Figure 3-4

BookTitle, Rev. #Freescale Semiconductor v 5 General Purpose Input/Output Port (GPIO)5.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . .

External Memory SupportDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 23-8 Freescale Semiconductor 3.5 External Memory SupportThe DSP5636

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 4-1 4 Core Configuration4.1 IntroductionThis chapter contains DSP

Operating Mode Register (OMR)DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 24-2 Freescale Semiconductor 4.2.1 Mode C (MC) - Bit 2The Mod

Operating ModesDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 4-3 4.3 Operating ModesThe operating modes are as

Bootstrap ProgramDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 24-4 Freescale Semiconductor address to start loading the program words a

Interrupt Priority RegistersDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 4-5 The interrupt vectors are shown i

Interrupt Priority RegistersDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 24-6 Freescale Semiconductor Figure 4-2 Interrupt Priority Re

DMA Request SourcesDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 4-7 4.6 DMA Request SourcesThe DMA Request Sou

Device Identification (ID) RegisterDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 24-8 Freescale Semiconductor 4.7.2 Crystal Range Bit (X

JTAG Boundary Scan Register (BSR)DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 4-9 4.10 JTAG Boundary Scan Regi

BookTitle, Rev. #vi Freescale Semiconductor 6.3.2.4 TCR ESAI Transmit 3 Enable (TE3) - Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JTAG Boundary Scan Register (BSR)DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 24-10 Freescale Semiconductor A12 Output3 DataSDO2/SDI3 -

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 5-1 5 General Purpose Input/Output Port (GPIO)5.1 IntroductionThe

GPIO Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 25-2 Freescale Semiconductor 5.2.1 Port B Control Register (PCRB)The

GPIO Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 5-3 Port B Direction Register (PRRB)The rea

GPIO Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 25-4 Freescale Semiconductor NOTES

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-1 6 Enhanced Serial AUDIO Interface (ESAI)6.1 IntroductionThe E

IntroductionDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-2 Freescale Semiconductor Figure 6-1 ESAI Block DiagramSDO1 [PC10]SDO0 [PC

ESAI Data and Control PinsDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-3 6.2 ESAI Data and Control PinsThree

ESAI Data and Control PinsDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-4 Freescale Semiconductor 6.2.4 Serial Transmit 3/Receive 2 D

ESAI Data and Control PinsDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-5 When this pin is configured as seri

BookTitle, Rev. #Freescale Semiconductor vii 6.3.5.1 SAICR Serial Output Flag 0 (OF0) - Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ESAI Data and Control PinsDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-6 Freescale Semiconductor SCKT may be programmed as a general

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-7 6.2.10 Frame Sync for Transmitter (FST)

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-8 Freescale Semiconductor special-purpose time slot register. The

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-9 Figure 6-3 ESAI Clock Generator Functi

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-10 Freescale Semiconductor operational (see Figure 6-3). The maxi

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-11 Figure 6-4 ESAI Frame Sync Generator

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-12 Freescale Semiconductor 6.3.1.5 TCCR Transmit Clock Polarity (

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-13 6.3.2 ESAI Transmit Control Register (

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-14 Freescale Semiconductor In the network mode, the operation of

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-15 transmitter #4 is disabled after compl

BookTitle, Rev. #viii Freescale Semiconductor 6.6.2 Initializing Just the ESAI Transmitter Section . . . . . . . . . . . . . . . . . . . . . . . . . .

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-16 Freescale Semiconductor Since the data word is shorter than th

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-17 Figure 6-6 Normal and Network Operati

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-18 Freescale Semiconductor 6.3.2.10 TCR Tx Slot and Word Length S

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-19 6.3.2.11 TCR Transmit Frame Sync Lengt

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-20 Freescale Semiconductor Figure 6-7 Frame Length SelectionDATA

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-21 6.3.2.12 TCR Transmit Frame Sync Relat

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-22 Freescale Semiconductor 6.3.2.17 TCR Transmit Even Slot Data I

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-23 Hardware and software reset clear all

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-24 Freescale Semiconductor The ESAI frame sync generator function

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-25 6.3.3.8 RCCR Receiver Clock Source Dir

BookTitle, Rev. #Freescale Semiconductor ix 7.6.2 I2C Data Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-26 Freescale Semiconductor 6.3.3.10 RCCR Receiver High Frequency

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-27 receivers can be enabled) if the input

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-28 Freescale Semiconductor 6.3.4.4 RCR ESAI Receiver 3 Enable (RE

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-29 6.3.4.9 RCR Receiver Slot and Word Sel

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-30 Freescale Semiconductor 6.3.4.10 RCR Receiver Frame Sync Lengt

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-31 6.3.4.12 RCR Receiver Section Personal

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-32 Freescale Semiconductor 6.3.5 ESAI Common Control Register (SA

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-33 6.3.5.5 SAICR Synchronous Mode Selecti

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 26-34 Freescale Semiconductor Figure 6-11 SAICR SYN Bit Operation6.

ESAI Programming ModelDSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2Freescale Semiconductor 6-35 6.3.6.1 SAISR Serial Input Flag 0 (IF0